1. Field of the Disclosure
Generally, the present disclosure relates to the technology of semiconductor devices including metallization systems and a pad structure for connecting to a package.
2. Description of the Related Art
Semiconductor devices typically include, depending on the degree of complexity, a more or less number of semiconductor-based circuit elements, such as field effect transistors, bipolar transistors and the like, typically in combination with resistors, capacitors and the like. In most approaches, these circuit elements may be formed in and on a corresponding semiconductor layer, such as a silicon layer, a silicon/germanium layer or any other appropriate semiconductor material layer, wherein, layer after layer, respective device patterns may be formed and/or processed in accordance with a specified design and related design rules by using well-established, yet sophisticated, manufacturing techniques, such as photolithography, etching, ion implantation and the like. Depending on the overall complexity of the semiconductor device under consideration, a relatively high number of process steps may be necessary so as to complete a functional device. For example, in the so-called “front end of line” (FEOL), respective process steps are performed in order to complete the actual semiconductor-based circuit elements, such as transistors and the like, wherein, in sophisticated applications, transistor elements of critical dimensions of 30 nm and less may be manufactured, thereby providing the potential for implementing a very large number of circuit elements and, thus, configuring entire systems in a single chip. Thereafter, the previously formed semiconductor-based circuit elements, such as transistors, resistors and the like, may be passivated and may be particularly interconnected with each other by providing so-called contact elements, which may be formed in appropriate dielectric material(s) formed so as to reliably cover the previously fabricated circuit elements.
Next, a metallization system has to be formed by providing appropriate dielectric materials and forming therein metal and contact vias, thereby providing “a fabric” of highly conductive metal-containing connections, similar to a multilevel printed circuit board, in order to establish the required electrical connections for obtaining the desired functional behavior. Generally, in complex metallization systems, two or more metallization levels may have to be implemented in order to provide the required number of electrical connections between the individual circuit elements, since, typically, the number of required connections increases over-proportionally with respect to the number of circuit elements implemented in the device level.
Furthermore, since the electrical connections in the metallization system may have a significant influence on the overall performance of the completed semiconductor device, sophisticated materials and techniques have been developed in order to form highly conductive metal lines and vias with reduced lateral dimensions, yet high performance, thereby typically requiring the incorporation of highly conductive metals, such as copper, copper alloy and the like, in combination with appropriately designed materials, such as so-called low-k dielectric materials having a dielectric constant of 3.7 and lower. Consequently, in many cases, the resulting metallization system represents a complex stack of metallization layers, at least some of which may be formed on the basis of critical materials suffering from less pronounced mechanical stability compared to conventional dielectric materials, such as silicon dioxide, silicon nitride and the like. Consequently, when encountering certain loads during the further processing or during operation of such semiconductor devices, including respective metallization systems, yield loss and/or premature failure of semiconductor devices may be observed, which may be frequently caused by cracks forming in sensitive dielectric materials, which may not only result in a reduction of mechanical stability, but may also impart less electrical strength to respective portions of the metallization system.
Frequently, substantial mechanical stress may be introduced into the sensitive metallization system by interaction with a final layer or passivation level connecting to and passivating the metallization system, which may comprise an appropriate passivation material providing the required robustness with respect to environmental conditions and the like, and which may also have formed therein respective contact pads that may serve for connecting the semiconductor device under consideration to other components, such as a package, any other appropriate carrier material, other semiconductor devices so as to form three-dimensional chip configurations, and the like. That is, the arrangement of respective contact pads is designed so as to provide communication to the outside world with respect to mechanical, electrical and thermal interaction with the environment. For example, one frequent approach for providing communication of the semiconductor device with the environment is the incorporation of the semiconductor chip into a package and providing electrical contact to the package or pins thereof by means of wire bonding, in which appropriate metallic wires, such as copper wires and the like may be connected to the respective contact pads, also referred to as bond pads, by applying pressure and heat. For example, wire bonding has become a very established and economic technology for semiconductor devices in which, irrespective of the internal complexity, a relatively restricted number of contacts to the environment is required.
In other contact technologies, an electrical and mechanical contact between the semiconductor device and a carrier or package substrate may be established by soldering techniques in which respective solder bumps may be provided in at least one of the package substrates and the semiconductor device, while the actual connection may be established on the basis of a soldering process. Also, in this case, significant mechanical stress may be induced in the passivation level of the semiconductor device, which may comprise polyimide and the like, having superior passivation characteristics, yet exhibiting a relatively brittle behavior when exposed to mechanical stress. Consequently, in the arrangement of respective contact pads, which may be frequently formed of aluminum, stress may be created, for instance, in the form of tensile stress, frequently promoted by the significant difference of the coefficients of thermal expansion between the aluminum contact pads and the surrounding passivating dielectric material. Respective cracks may then propagate under the influence of the tensile stress and may reach deeper lying metallization layers, in particular when sophisticated dielectric materials may have been used therein. As discussed above, any such crack-related defects in the metallization system may result in yield loss, premature failure or reduced reliability of the semiconductor device under consideration.
In many approaches, the respective contact pads may have to be placed with tight spacing in the passivation level so as to comply with design criteria such that, for instance, providing respective bond pads as substantially “isolated” structures for enhancing mechanical robustness may not represent a viable option. In other cases, in addition to contact pads, relatively thick metal lines, for instance for RF applications, may have to be frequently implemented, thereby exacerbating the problem of crack formation in the passivation layer and underlying metallization layers even further.
For example, U.S. Pat. No. 8,860,224 discloses a semiconductor device wherein an ultra-thick metal (UTM) line is formed over the top metal layer, wherein a passivation material is formed so as to exhibit a specific thickness compared to the metal layer in an attempt to reduce metallization failures.
U.S. Patent Publication No. 2013/0320522 discloses a semiconductor device with a contact pad formed over a substrate, wherein a via in a first passivation layer is formed so as to connect the contact pad to a metal region of the last metallization layer on the basis of a specifically designed via geometry.
U.S. Patent Publication No. 2015/0061156 discloses a manufacturing technique for forming a bond pad, for instance, for wire bonding, by reducing the number of dielectric layers in the passivation level of the semiconductor device, however, without specifically addressing the problem of crack formation in the passivation material and the metallization layers positioned below the passivation layer.
In view of the situation described above, the present disclosure, therefore, relates to semiconductor devices and manufacturing techniques in which contact pads, such as bond pads and the like, may be formed in a passivating material, while avoiding or at least reducing the effects of one or more of the problems identified above.